With the rise of Artificial Intelligence (AI), Machine Learning (ML) and the Internet of Things (IoT), applications are moving to the network edge where data is collected, requiring power-efficient solutions to deliver more computational performance in ever smaller, thermally constrained form factors. Through its Smart Embedded Vision initiative, Microchip Technology Inc. (Nasdaq: MCHP) is meeting the growing need for power-efficient inferencing in edge applications by making it easier for software developers to implement their algorithms in PolarFire® field-programmable gate arrays (FPGAs). As a significant addition to the solutions portfolio in this segment, Microchip’s VectorBlox Accelerator Software Development Kit (SDK) helps developers take advantage of Microchip’s PolarFire FPGAs for creating low-power, flexible overlay-based neural network applications without learning an FPGA tool flow.
FPGAs are ideal for edge AI applications, such as inferencing in power-constrained compute environments, because they can perform more giga operations per second (GOPS) with greater power efficiency than a central processing unit (CPU) or graphics processing unit (GPU), but they require specialized hardware design skills. Microchip’s VectorBlox Accelerator SDK is designed to enable developers to code in C/C++ and program power-efficient neural networks without prior FPGA design experience.
The highly flexible tool kit can execute models in TensorFlow and the open neural network exchange (ONNX) format which offers the widest framework interoperability. ONNX supports many frameworks such as Caffe2, MXNet, PyTorch, and MATLAB®. Unlike alternative FPGA solutions, Microchip’s VectorBlox Accelerator SDK is supported on Linux® and Windows® operating systems, and it also includes a bit accurate simulator which provides the user the opportunity to validate the accuracy of the hardware while in the software environment. The neural network IP included with the kit also supports the ability to load different network models at run time.
“In order for software developers to benefit from the power efficiencies of FPGAs, we need to remove the impediment of them having to learn new FPGA architectures and proprietary tool flows, while giving them the flexibility to port multi-framework and multi-network solutions,” said Bruce Weyer, vice president of the Field Programmable Gate Array business unit at Microchip. “Microchip’s VectorBlox Accelerator SDK and neural network IP core will give both software and hardware developers a way to implement an extremely flexible overlay convolutional neural network architecture on PolarFire FPGAs, from which they can then more easily construct and implement their AI-enabled edge systems that have best-in-class form factors, thermals and power characteristics.”
For inferencing at the edge, PolarFire FPGAs deliver up to 50 percent lower total power than competing devices, while also offering 25 percent higher-capacity math blocks that can deliver up to 1.5 tera operations per second (TOPS). By using FPGAs, developers also have greater opportunities for customization and differentiation through the devices’ inherent upgradability and ability to integrate functions on a single chip. The PolarFire FPGA neural network IP is available in a range of sizes to match the performance, power, and package size tradeoffs for the application, enabling customers to implement their solutions in package sizes as small as 11 × 11 mm.
Microchip’s Smart Embedded Vision initiative was launched last July to provide hardware and software developers with tools, intellectual property (IP) cores, and boards for meeting the thermally constrained and small-form-factor requirements of edge applications. Because PolarFire FPGAs deliver lower power compared to other solutions, customers can eliminate the need for fans in their enclosures. PolarFire FPGAs also offer more functional integration for a customer’s design. For example, in applications such as a smart camera, PolarFire FPGAs can integrate the image signal pipeline which includes the sensor interface, DDR controller, image signal processing (ISP) IP and network interfaces, all while integrating the machine learning inference.
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